1. Field of the Invention
The present invention relates to a semiconductor device comprising a semiconductor substrate and an insulating layer which may serve as a primary insulating film for passivating active regions formed in the semiconductor substrate, an interlayer-insulating film provided between metal wiring layers and a final insulating film applied on an uppermost surface of the semiconductor device. The invention also relates to a method of manufacturing such an insulating layer.
2. Description of the Related Art
The final passivation film applied on the uppermost surface of a semiconductor device should have such properties that the introduction of impurities into a semiconductor chip can be prevented and the impurities are held in the passivation film due to its gettering effect. Further, it is required that the insulating film be formed at a low temperature and have excellent mechanical, physical and chemical properties.
It has been proposed to form the final insulating layer by a PSG (phosphosilicate glass) film which has a good gettering function for alkali ions and which can be formed at a lower temperature. However, it is well known that the PSG film has poor moisture resistance and waterproof properties. It is also known to use a plasma-CVD silicon nitride film as the final insulating film. This plasma-CVD silicon nitride film can be formed at a low temperature and has excellent mechanical and chemical blocking properties. However, the plasma-CVD silicon nitride film has a poor gettering effect. In order to compensate the above-mentioned drawbacks of the known insulating film, it has been further proposed to use a double-layer final insulating layer in which a plasma-CVD silicon nitride film is formed on a PSG film. Such a final passivation film is disclosed in Japanese Patent Application Laid-open Publications Kokai Sho 60-214534 and 63-84122.
FIG. 1 is a cross-sectional view showing the above-mentioned known semiconductor device in which the final insulating layer is formed by a double-layer of a PSG film and a plasma-CVD silicon nitride film. As illustrated in FIG. 1, an aluminum wiring pattern 1 is formed on an insulating film in the form of protrusions and a PSG film 2 is formed on the wiring pattern 1. A plasma-CVD silicon nitride film 4 is formed on the PSG film 2. The PSG film 2 does not have a sufficient step coverage due to its low flattening characteristic. Therefore, when the PSG film 2 is formed on the aluminum wiring pattern 1, there are formed overhangs 3 corresponding to the protrusions of the wiring pattern 1. Moreover, the plasma-CVD silicon nitride film 4 formed on the PSG film 2 has similar overhangs 5 as those of the underlying PSG film 2. At these overhangs 3 and 5, the thickness of the insulating layer, particularly the upper plasma-CVD silicon nitride film, becomes very thin. The plasma-CVD process for forming the plasma-CVD silicon nitride film 4 is generally carried out by utilizing a parallel electrode type plasma CVD apparatus. The movement of ions is predominantly limited to the up and down direction, so that the plasma-CVD silicon nitride film 4 is liable to be porous, and thus it does not have sufficient moisture resistance and waterproof properties necessary for the final passivation layer. This results in a serious deterioration in the reliability of the semiconductor device. Similar drawbacks would equally occur in the primary insulating layer and interlayer-insulating film.
In order to mitigate the above-explained drawback, it is proposed to increase the thickness of the upper plasma-CVD silicon nitride film. However, this solution might cause another problem because the plasma-CVD silicon nitride has a large residual stress, so that the thick silicon nitride film might cause the aluminum wiring pattern to deform and break, introducing cracks and aluminum slide into the semiconductor device. Further, it would be difficult to obtain the required precision for etching pads. Moreover, there might be a problem in the anti-plasma property against the resist for use in the pad etching.